The present invention disclosed herein relates to a semiconductor memory device and more particularly, to a memory system including a flash memory device.
In recent years, applications of storage devices, such as volatile memories and nonvolatile memories, are rapidly spreading into mobile apparatuses such as MP3 players, PMPs, mobile phones, notebook computers, PDAs, and the like. Such mobile apparatuses increasingly necessitate large volume storage capacity in order to provide various functions, such as moving picture reproducing functions. Various efforts have been made to satisfy such needs. As one of the efforts, a multi-bit memory device has been proposed which stores 2 or more data bits in one memory cell. Exemplary multi-bit memory devices for storing multi-bit data in one memory cell are disclosed in U.S. Pat. No. 6,122,188 entitled “NON-VOLATILE MEMORY DEVICE HAVING MULTI-BIT CELL STRUCTURE AND A METHOD OF PROGRAMMING SAME”, U.S. Pat. No. 6,075,734 entitled “INTEGRATED CIRCUIT MEMORY DEVICE FOR STORING A MULTI-BIT DATA AND A METHOD FOR READING STORED IN THE SAME”, and U.S. Pat. No. 5,923,587 entitled “MULTI-BIT MEMORY CELL ARRAY OF A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME”, the entire contents of which are hereby incorporated by reference.
In a case where a memory cell stores 1-bit data, it has a threshold voltage in either one of two threshold voltage distributions. That is, a memory cell has either one of two states indicating data ‘1’ and data ‘0’, respectively. On the other hand, in the case that a memory cell that stores 2-bit data, it has a threshold voltage in one of four threshold voltage distributions. That is, a memory cell has one of four states indicating data ‘11’, data ‘10’, data ‘01’ and data ‘00’, respectively.
A method for programming multi-bit data in a memory cell can be implemented in various ways. For example, two data bits stored in each memory cell consists of page data (hereinafter, referred to as LSB (least significant bit) data (or, lower data) and MSB (most significant bit) data (or, upper data)), respectively. In this case, firstly, an LSB data bit is programmed in a memory cell, and then an MSB data bit is programmed in the memory cell. Hereinafter, this manner of programming a multi-data in a memory is called page unit programming, which will be more fully described below.
One memory cell can be programmed to have one of ‘11’, ‘10’, ‘00’ and ‘01’ states. For convenience, it is assumed that the ‘11’, ‘10’, ‘00’ and ‘01’ states correspond to ST0, ST1, ST2 and ST3, respectively. A memory cell having a ‘11’ state is an erased memory cell, and a threshold voltage of a memory cell having a ‘10’ state is higher than that having a ‘11’state. A threshold voltage of a memory cell having a ‘00’ state is higher than that having a ‘10’ state, and a threshold voltage of a memory cell having a ‘01’ state is higher than that having a ‘00’ state. If an LSB program operation is made under the assumption, as illustrated in FIG. 1A, that a memory cell has an erased state or a ‘10’ state (ST1). If there is performed an MSB program operation following the LSB program operation, as illustrated in FIG. 1B, a memory cell having a ‘11’ state has an erased state or a ‘01’ state (ST3), while a memory cell having a ‘10’ state (ST1) has a ‘10’ state (ST1) or a ‘00’ state (ST2). That is, a memory cell is programmed into a ‘01’ state when LSB data is ‘1’, while it is programmed into a ‘00’ state when LSB data is ‘0’.
One problem arises when storing multi-bit data, which will be more fully described below.
For convenience of description, there will be described an operation of storing 2-bit data in one memory cell. As described above, firstly, a lower data bit can be stored in a memory cell. And then, an upper data bit can be stored in the memory cell. In a case where a power is turned off while an upper data bit is programmed in a memory cell, a program operation of a finally programmed page at power-up is cancelled. On the other hand, assuming that a power is turned off while an upper data bit is programmed in a memory cell, a previously stored lower data bit can be lost. This is because a threshold voltage corresponding to a lower data bit is varied at a program operation of an upper data bit.